In recent years a technology has been developed to use low-k film (low dielectric constant film), which exhibits a low relative dielectric constant, in place of SiO2 film in semiconductor devices. With this technological development, it has become necessary to etch low-k film in the production process of semiconductor devices. Conventionally, after the film is subjected to dry etching, O2 plasma ashing is performed to remove the resist; however, such a treatment may damage low-k film. It is, therefore, desirable to remove resist with a chemical solution, without O2 plasma ashing (or after carrying out H2 plasma ashing or light O2 plasma ashing). However, the resist-removing solutions proposed heretofore cannot be used for such a purpose because they fail to remove the resist (for example, KRF (Krypton F) resist) itself formed on low-k film while they etch the low-k film.
In the production process of a semiconductor device, after forming via holes, titanium compounds and/or polymers may remain on the sidewalls and/or the bottoms of the via holes. The development of a composition is therefore desired that can be used to remove such titanium compounds and/or polymers from via holes.
Furthermore, in the formation of a metal capacitor in the semiconductor device production process, polymers, resist residue, and titanium compounds may remain after the dry etching of an upper or lower electrode metal film (TiN, Ti, etc.) of the metal capacitor. The development of a composition is therefore desired that can be used to remove such polymers, resist residue, and titanium compounds.
Until recently, semiconductor devices with an Al/SiO2 multilevel interconnection structure have mainly been produced, which use aluminum, aluminum alloy or the like as a wiring material, and a SiO2 film as an interlayer dielectric. In order to reduce the wiring delay caused by the microminiaturization of devices, semiconductor devices with a Cu/low-k multilevel interconnection structure are now being developed, which use Cu as a wiring material having low resistance; and low-k film (low dielectric constant film) as an interlayer dielectric having low interconnect capacitance, in place of the SiO2 film.
In the Al/SiO2 multilevel interconnection structure, wiring layers and via layers are separately formed; the wiring layers supplying electric current horizontally to a processed wafer; and the via layers forming the wiring through vertical holes that connect the wiring layers. Each wiring layer is formed by producing convex metal wiring (such as Al) by metal dry etching, and depositing an interlayer dielectric such as SiO2 film to embed the wiring. After the deposition of an interlayer dielectric such as SiO2 film, the via layer is formed by subjecting the interlayer dielectric to dry etching to form a hole (via hole), and filling the hole with a metal such as Al or W.
The Cu/low-k multilevel interconnection structure is produced by a process called damascene, wherein the wiring structure is obtained by forming a trench or a hole (via hole) in low-k film by dry etching, and then filling the trench or hole with a wiring material such as copper. In the method called dual damascene, trenches for wiring and via holes are formed in low-k film at the same time, and then filled with a wiring material such as copper. A dual damascene structure can be formed by a via-first process, wherein the via holes are formed prior to the trenches for wiring; or conversely, by a trench-first process, wherein the trenches for wiring are formed prior to the via holes; or by other processes such as a middle-first process or a dual hard mask process. In the dual damascene process or the like, a filling material is used in many cases. In the via-first process, for example, via holes are formed by dry etching and then filled with a filling material, followed by lithography and etching for the formation of trenches. Thereafter the filling material must be selectively removed.
In the Al/SiO2 multilevel interconnection structure, the metal etching for the formation of wiring uses a gas such as chlorine or hydrogen bromide, and the via etching for the formation of via holes uses a mixed gas of fluorocarbon gas, hydrofluorocarbon gas, an inert gas such as Ar, oxygen, an oxygen-containing gas such as carbon monoxide, etc. After metal etching or the via etching of the interlayer dielectric for via hole formation, ashing is performed using an oxygen-containing plasma to remove unnecessary substances such as resist and etching residues. The residue remaining after ashing is removed using a removing solution. In the case of metal etching, the residue consists of oxides of aluminum, etc., that contain a small amount of organic substances such as resist. Since this residue is formed on the sidewalls of aluminum wiring, it may be referred to as “sidewall polymer,” “rabbit ear,” and so on. In the case of via etching, the residue consists of oxides or fluorides of Ti, TiN, or other metal barrier films that contain a small amount of organic substances such as resist and fluorocarbon polymers. This residue may also be referred to as “sidewall polymer.” In many cases the residue after metal or via hole etching is subjected to an ashing treatment until the resist is removed using oxygen plasma, with the result that the principal component of the etching residue is an oxide that has been made inorganic.
In the Cu/low-k multilevel interconnection structure, by contrast, the damascene structure of a trench or a via hole in low-k film is formed by dry etching using a fluorocarbon gas mixed with nitrogen, etc. The use of nitrogen in the dry etching gas enhances processing accuracy. However, reaction of the gas with low-k film containing silicon forms a residue of nonvolatile nitrided silicon. If ashing is completely performed using an oxygen-containing plasma to remove the resist and residue after etching, the low-k film will be damaged, causing a change in dielectric constant. This kind of plasma ashing, therefore, is not performed in many cases; instead, ashing may be carried out with a plasma of hydrogen, nitrogen, noble gas, a mixture of these gases, or the like, or light ashing may be carried out with an oxygen-containing plasma. Also, in many cases, to minimize the damage to the low-k film, the resist and filling material are not completely removed by ashing. If a nitrogen-containing gas is used for plasma ashing, the residue contains further nitrided silicon in a large amount. In such a case, even after ashing, a relatively large amount of resist, antireflection coating, filling material, and nitrogen-containing etching residue such as silicone nitride are present. Even if ashing is carried out to a considerable extent, it is difficult to remove all of the resist, antireflection coating, and filling material. As a result, the principal component of the residue present after etching in the damascene process is an organic substance that originates in the resist, antireflection coating, filling material, and fluorocarbon polymer, and contains an inorganic substance such as silicon nitride.
There have been many patent applications filed for removing solutions that can be used to remove the mineralized residue produced by dry etching in the process of forming an Al/SiO2 multilevel interconnection structure; and for cleaning solutions that can be used to clean the formed pattern. Japanese. Unexamined Patent Publication No. 1989-146331 discloses a cleaning solution obtained by mixing hydrofluoric acid with an organic solvent such as isopropanol, and mentions that this cleaning solution enhances wettability and uniformity in cleaning. However, it does not refer to the removal of dry etching residue or resist, which the present invention deals with. Japanese Patent No. 3255551 discloses a resist-removing composition that contains at least one anticorrosive selected from the group consisting of HF, water-soluble organic solvents, aromatic hydroxy compounds, acetylene alcohols, carboxyl-containing organic compounds and anhydrides thereof, and triazole compounds. It mentions sulfoxides, amides, polyhydric alcohols, etc., as effective organic solvents. According to Japanese Unexamined Patent Publication No. 1998-50647, after the formation of a contact hole, the contact hole is cleaned by carefully etching the native oxide at the bottom of the contact hole and the oxide on the sidewalls thereof containing pollutants such as etching residues and metal substances. It discloses that when a contact hole formed by penetrating three kinds of films, i.e., a plasma silicon oxide film, a low-pressure chemical vapor deposition silicon oxide film, and a BPSG film, is cleaned in a mixed solution of a low concentration (about 0.25% to about 0.5% by weight) of hydrogen fluoride, isopropanol, and DIW (deionized water), the contact hole obtains an uniform profile without level differences. U.S. Pat. No. 6,150,282 discloses the use of hydrogen fluoride and an organic solvent for providing a cleaning solution and a cleaning method for etching residue after the formation of a via hole in a silicon oxide film. It discloses a method of removing and etching at least one of a mask, an etching residue, a silicon oxide film, and a silicon nitride film, using a removing solution containing hydrogen fluoride, an organic solvent, and water. Japanese Unexamined Patent Publication No. 1999-340183 discloses a cleaning solution containing 20% or less by weight of hydrogen fluoride, an alcohol with a dielectric constant of 10 or more, etc., which can be used for cleaning after via hole etching or for removing sidewall polymers after the dry etching of metal wiring while inhibiting the corrosion of the metal wiring of aluminum, etc.
The above inventions, however, do not consider the use of low-k film as an interlayer dielectric, and copper as a wiring material. They are intended to remove inorganic residue after dry etching or to clean the formed pattern, in the formation of an Al/SiO2 multilevel interconnection structure.
A principal object of the present invention is to provide a resist-removing solution for low-k film, a cleaning solution for via holes, and a cleaning solution for metal capacitors.